Hardware Farm Technician

Role Proficiency:

Ability to e xecute any small to mid size customer project in any field of VLSI Frontend Backend or Analog design with minimal supervision

Outcomes:

1. Work as an individual contributor to own any one task of RTL Design/Module and provide support to junior engineers in Verification/PD/DFT/Circuit Design/Analog Layout/STA/Synthesis/Design Checks/Signoff etc.
2. Independently analyze and complete the assigned task in the defined domain(s) successfully and on-time
3. On time quality delivery approved by the project lead/manager

Measures of Outcomes:

1. Quality -verified using relevant metrics by Lead/Manager
2. Timely delivery - verified using relevant metrics by Lead/Manager
3. Reduction in cycle time and cost using innovative approaches
4. Number of trainings attended
5. Number of new projects handled

Outputs Expected:

Quality of the deliverables:

1. Ensure clean delivery of the design and module in-terms of ease in integration at the top level
2. Meet functional spec / design guidelines 100% of the time without any deviation or limitation
3. Documentation of the tasks and work performed

Timely delivery:

1. Meeting project timelines as requested by the program manager
2. Support the team lead in intermediate tasks delivery

Team Work:

1. Participation in team work; supporting team members/lead at the time of need
2. Able to perform additional tasks in-case any team member(s) is not available

Innovation & Creativity:

1. Automate repeated tasks to save design cycle time as a necessary approach
2. Participation in technical discussion
   training
   forum

Skill Examples:

1. Languages and Programming skills:a. System Verilog Verilog VHDL UVM C C++ Assembly Perl TCL/TK Makefile Spice (any one)
2. EDA Tools: a. Cadence Synopsys Mentor tool sets (one or more)b. Simulators Lint CDC/RDC DC/RTL-C ICC/Innovus/Olympus ETS/TK/FS PT/Tempus Calibre etc. (any one)
3. Technical Knowledge: (any one)a. Partially implement IP Spec Architecture Design Micro Architecture Functional Spec Test Plan Verificationb. Strong in Bus Protocol AHB/AXI/PCIe/USB/Ethernet/SPI/I2C Microprocessor architecturec. Strong knowledge in Physical Design / Circuit Design / Analog Layout d. Strong understanding of Synthesis DFT Floorplan Clocks P&R STA Extraction Physical Verificatione. Strong knowledge of Soft / Hard / Mixed Signal IP Design Processor Hardening FPGA Design
4. Technology: CMOS FinFet FDSOI - 28nm / 22nm / 16ff / 10nm and below
5. Strong communication skills
6. Good analytical reasoning and problem-solving skills with attention to details
7. Able to deliver the tasks on-time per quality guidelines and GANTT in every instance.
8. Required technical skills and prior design knowledge to execute the assigned tasks
9. Ability to learn new skills in-case required technical skills are not present to a level needed to execute the project

Knowledge Examples:

• Frontend / Backend / Analog Design:a. Project experience in any of the design by executing any one of - RTL Design / Verification / DFT / Physical Design / STA / PV / Circuit Design / Analog Layout etc.b. Strong understanding of the design flow and methodologies used in designing
• Understanding of the technical specs and assigned tasks:
• Understand the assigned tasks and have strong knowledge to execute the project tasks assigned by the client / manager as per shown skill
  
  Additional Comments:
  
  

  Job Title: Standard Cell Layout Engineer Location: [ Bangalore ] Experience: [2-8 Years] Job Description: Key Responsibilities: * Perform physical layout design of standard cells and library development to meet performance, area, and power targets. * Work closely with circuit designers to translate schematics into optimized layouts. * Perform floor planning, placement, routing, and device-level layout for standard cells ensuring adherence to design rules (DRC) and layout vs schematic (LVS) checks. * Optimize layouts for high density, performance, and manufacturability. * Conduct parasitic extraction and analysis to meet circuit performance requirements. * Support layout verification, QA, and signoff processes. Required Skills: * Strong knowledge of CMOS technology, layout techniques, and design rules. * Experience in standard cell layout development (basic logic gates, sequential cells, complex cells). * Proficiency in Cadence Virtuoso, Calibre, or similar layout and verification tools. * Good understanding of DRC, LVS, ERC, and parasitic extraction flows. * Ability to work collaboratively in a cross-functional environment with circuit designers and methodology teams. * Attention to detail, strong problem-solving skills, and ability to meet tight schedules. Preferred Qualifications: * Experience in advanced technology nodes (7nm / 5nm / 3nm). * Familiarity with layout automation techniques and scripting (SKILL, Perl, Python). * Exposure to EDA flow enhancements and layout methodologies. Education: * B.E./B.Tech/M.Tech in Electronics, Electrical, or VLSI Design.

  
  

Standard cell layout,Circuit Design,EDA Flow