Senior Principal Validation Engineer - SERDES

About Marvell

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

What You Can Expect

Marvell is seeking an experienced Senior Principal SERDES signal integrity engineer to lead the validation for SERDES IP in the Data Center Hardware Engineering Group. In this role you will:

• Own the electrical characterization/compliance of SERDES IP for PCIe, Networking (Ethernet). Develop and implement test plans for SERDES characterization.

• Develop methods for automated electrical characterization (validation) of the interfaces. Develop standard test methods and regression tests for the validation of the IPs.

• Plan equipment (CAPEX) and resource needs for supporting the BU products.

• Develop the technical skillset in the team to handle complex SERDES debugging issues.

• Represent Marvell's interest at the standards committees and be an active contributor on these committees. Ensure that our planning for future SERDES IP is well addressed from an equipment and training perspective.

• Support high-speed board design, debug and board extraction, definition and characterization for the SERDES devices as well as collaborate with the internal tools engineering team to design the test infrastructure.

• Must have proven ability to work with executive management to develop and implement long term solutions impacting the success of the business group.

What We're Looking For

• Bachelor's degree in Computer Science, Electrical Engineering or related fields and 15+ years of related professional experience. OR Master's degree in Computer Science, Electrical Engineering or related fields with 10+ years of experience. OR PhD in Computer Science, Electrical Engineering or related fields with 8+ years of experience.
  5+ years of direct experience in SERDES characterization and design.

• In depth knowledge of SERDES interface using NRZ and PAM4 signaling for Ethernet and PCIe interfaces, knowledge of relevant Ethernet standards (e.g., 10GbE, 100GbE, 400GbE)is a plus.

• In depth working knowledge of test equipment used for SERDES characterization (Scope, BERT, Network analyzer etc.).

• Deep understanding of high-speed electrical signaling principles, differential signaling and mixed-signal designs.

• Experience in Python programming language for automation framework development, as well as mathematical programing such as Matlab.

• Critical thinking and problem-solving attitude and ownership of the group's results.

• Knowledge in SERDES modeling techniques

• Excellent verbal and written communication skills.

Expected Base Pay Range (USD)

The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.